This invention relates generally to the testing of very large scale integrated (VLSI) circuits and in particular to mode programmable data registers for performing on-chip self-test in a semiconductor device.
With the increasing complexity of VLSI chips, most modern design approaches are hierarchical and modular in concept. In such cases the chip design generally results in groups of reasonably large functional elements that are interconnected in a "pipeline" format through data storage or transfer registers. In fact the main inputs to and outputs from the chip are parallel data registers. Considering the complexity of such chips, the overall testing using the I/O ports as an interface to large commercial testers represents a formidable task.
Considering the amount of combinatorial logic being exercised in a VLSI chip and the myriad of possible fault modes, it has been estimated by many skilled in the art that millions of test generated inputs and observed outputs must be accomplished in order to state with confidence that a semiconductor chip is "good". Because of this, a great deal of attention has been given in the past few years to techniques for most optimally and efficiently testing a VLSI chip. Various techniques are described in "Built-In Self-Test Techniques" by Edward J. McCluskey, IEEE Design and Test of Computers, Vol. 2, No. 2, pp. 21-28, Apr. 1985.
One such technique involves an approach for chip "self-test". In fact, it is a modern version of a technique devised earlier and applied to module-level testing of functional elements at the printed-circuit board, or higher levels. Using this technique, a series of Pseudo-Random Numbers (PRN) is applied to a functional element or elements and the response is cumulatively observed using a process of data compression or "Signature Analysis", SA.
With respect to applying the on-chip self-test technique to testing a VLSI chip, the current approach is to include the PRN generation on the chip as well as the signature analysis (SA). These elements are designed separately, and during the chip design appropriate control logic is included so that, when in a self-test mode, the PRN can be directed to any data register and the signature analyzer can collect data from any register. Typically, PRN generators are inserted serially to data registers and SA receivers capture data either serially or in parallel. After a number of pre-determined PRN inputs and SA data compressions, the results resident in the SA receiver are compared to a previously determined (from logic simulation) "signature".
The circuits for PRNG, SA, control, and known results are generally incorporated on a section of the chip and called the "chip testability logic" (CTL). Considering the amount of secondary function the CTL must accomplish, it generally tends to consume a large fraction of the usable area on the chip (20% or greater), thereby decreasing the area available for the primary function of the chip.